This invention relates to static random access memories (SRAMs), and more particularly to reducing active leakage power in SRAMs.
An SRAM cell may be implemented using a bistable flipflop. The flipflop includes, for example, two load elements, two storage transistors, and two access transistors. A direct current (DC) supply voltage is applied to the flipflop to retain data stored by the flipflop. The flipflop may be implemented using metal oxide semiconductor (MOS) or bipolar transistors.
As shown in FIG. 1, a conventional, full complementary MOS (CMOS) SRAM cell 100 includes six transistors. Pull-up transistors 101 and 102 may be implemented using, for example, p-channel MOS (PMOS) transistors. Access transistors 103 and 104 and storage transistors 105 and 106 may be implemented using, for example, n-channel MOS (NMOS) transistors.
The drains of the pull-up transistors 101 and 102 are connected to a source line 110. The source line 110 is connected to a DC supply voltage VDD.
Nodes 120 and 122 store a potential that indicates a state of the cell 100. If the potential stored at node 120 is high, then the potential at node 122 is low. Conversely, if the potential at node 122 is high, then the potential at node 120 is low. The DC supply voltage VDD is applied to the sources of the pull up transistors 101 and 102 to retain the potentials stored at the nodes 120 and 122. The two stable states stored at the nodes 120 and 122 may be defined as a logic xe2x80x981xe2x80x99 and a logic xe2x80x980.xe2x80x99
The gates of the access transistors 103 and 104 are connected to a word line 115. The drains of the access transistors 103 and 104 are connected to the bit lines 140 and 142, respectively. The sources of the access transistors 103 and 104 are connected to the nodes 120 and 122, respectively. A high potential on the write line 115 turns on transistors 103 and 104 to connect nodes 120 and 122 to the bit lines 140 and 142, so that the nodes 102 and 122 may be accessed.
One problem associated with SRAMs is active power leakage. If the cell 100 is in an active mode (i.e., the source line 110 of the cell 100 is maintained at the supply voltage VDD), several leakage currents result. For example, if a cell 100 has a high potential stored at node 120 and a low potential at node 122, then gate oxide leakage currents occur, as shown by the dotted arrows in FIG. 1. In addition, sub-threshold leakage currents occur in transistors 102 and 105, as shown by the solid bold arrows in FIG. 1.
Individually, the active power leakage of one cell 100 is relatively small. However, an SRAM array may include millions of cells 100. Taken as a whole, the leakage currents of multiple cells may result in substantial active power leakage for the array. Although some gate oxide power leakage and sub-threshold power leakage may be tolerated in SRAMS, as the number of SRAM cells 100 in an array continues to increase, active power leakage is only compounded. In addition, with each new generation of SRAMs, the physical size of the cells 100 is reduced to enable more cells 100 to be placed in an array. As the size of the cells 100 is reduced, there is a corresponding reduction in the thickness of the gate oxide layer. As the gate oxide layer becomes thinner, active gate oxide power leakage increases further compounding the problem in SRAMs.